Job Listing Description

Electric Design and Analysis Engineer 4

PDS Tech, Inc. is seeking a Electric Design and Analysis Engineer in Tukwila, WA.


  • Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.
  • Leads development of high-level and detailed designs consistent with requirements and specifications.
  • Leads reviews of testing and analysis activity to assure compliance to requirements.
  • Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.
  • Leads activities in support of Supplier Management with make/buy recommendations and other technical services.
  • Coordinates engineering support throughout the lifecycle of the product.
  • Plans research projects to develop concepts for future product designs to meet projected requirements.
  • Works under minimal direction.
  • We are seeking experienced integrated circuit (IC) layout engineers to implement custom analog/mixed-signal circuits in state-of-the-art CMOS (22nm) and SiGe semiconductor fabrication processes.
  • The qualified candidate will have experience performing custom IC layout to achieve tight matching, high speed, low noise, and low power consumption.
  • Circuits for custom layout may include analog or digital standard cells, resistors and capacitors, IO cells, ESD structures, and SRAM leaf cells.

Responsibilities include:

  • Working closely with IC / chip design team on block-level and chip-level floor-planning
  • Performing cell-level layout, block-level layout, and chip assembly
  • Performing physical verification including design rule checks (DRC), layout vs. schematic (LVS) checks, and electrical rule checks (ERC)
  • Perform / support parasitic extraction (PEX) and analysis
  • Drive continued improvement of layout practices and procedures

Education / Experience:    
  • This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship.
  • Bachelor, Master or Doctorate degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
  • 6+ years of experience in full-custom analog/mixed-signal IC layout
  • Thorough understanding of industry-standard electronic design automation (EDA) tools for IC layout and physical verification – e.g. those from Cadence, Mentor Graphics, and Synopsys
  • Experience with standard cell development and/or familiarity with structured, pitched, or arrayed layout
  • Knowledge of performance analog and high-power layout techniques
  • Experience exercising and debugging the IC verification flow (DRC, LVS, XOR, PEX, etc.)
  • Demonstrated successful IC designs implemented in advanced commercial semiconductor fabrication process technologies – e.g.. <22nm FinFET), silicon-on-insulator (SOI), and/or silicon germanium (SiGe) processes.
  • Experience with layout techniques for managing IR drop, RC delay, electro-migration, self heating and coupling capacitance

Preferred Qualifications:

  • Experience with Radiation-Hardened By Design (RHBD) layout techniques
  • Experience with scripting to automate IC layout (e.g. SKILL, Perl, Python)
  • Experience with experimental process technologies (e.g. Gate-all-around FETs (GAAFETs))
  • Active security clearance

Job Number: 2110133723
Job Location: Seattle, WA
Duration: 6 months
Input Date: 11/19/2021
Attention: Bryan Bui
660 SW 39TH ST STE 215

City, State: RENTON, WA 98057
Phone: 206/763-2840
800 Phone: 800/678-8644
Fax Phone: 206/763-3283

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