Job Listing Description

Elect Design and Analy Engr 4

Chipton-Ross is seeking 2 Electrical Design and Analysis Engr 4's for an opportunity in Tukwila, WA.

Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products. Leads development of high-level and detailed designs consistent with requirements and specifications. Leads reviews of testing and analysis activity to assure compliance to requirements. Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements. Leads activities in support of Supplier Management with make/buy recommendations and other technical services. Coordinates engineering support throughout the lifecycle of the product. Plans research projects to develop concepts for future product designs to meet projected requirements. Works under minimal direction.

We are seeking experienced integrated circuit (IC) layout engineers to implement custom analog/mixed-signal circuits in state-of-the-art CMOS (=22nm) and SiGe semiconductor fabrication processes. The qualified candidate will have experience performing custom IC layout to achieve tight matching, high speed, low noise, and low power consumption. Circuits for custom layout may include analog or digital standard cells, resistors and capacitors, IO cells, ESD structures, and SRAM leaf cells.
Tasks/responsibilities include:
Working closely with IC / chip design team on block-level and chip-level floor-planning
Performing cell-level layout, block-level layout, and chip assembly
Performing physical verification including design rule checks (DRC), layout vs. schematic (LVS) checks, and electrical rule checks (ERC)
Perform / support parasitic extraction (PEX) and analysis
Drive continued improvement of layout practices and procedures

6+ years of experience in full-custom analog/mixed-signal IC layout
Thorough understanding of industry-standard electronic design automation (EDA) tools for IC layout and physical verification e.g. those from Cadence, Mentor Graphics, and Synopsys
Experience with standard cell development and/or familiarity with structured, pitched, or arrayed layout
Knowledge of performance analog and high-power layout techniques
Experience exercising and debugging the IC verification flow (DRC, LVS, XOR, PEX, etc.)
Demonstrated successful IC designs implemented in advanced commercial semiconductor fabrication process technologies e.g.. <22nm FinFET), silicon-on-insulator (SOI), and/or silicon germanium (SiGe) processes. Experience with layout techniques for managing IR drop, RC delay, electromigration, self heating and coupling capacitance Preferred Qualifications: Experience with Radiation-Hardened By Design (RHBD) layout techniques Experience with scripting to automate IC layout (e.g. SKILL, Perl, Python) Experience with experimental process technologies (e.g. Gate-all-around FETs (GAAFETs)) EDUCATION: Accredited Bachelor, Master or Doctorate degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry. TRAVEL: YES Possible domestic trave WORK HOURS: 7:00AM-3:30PM Full-Time/First Shift ADDITIONAL INFORMATION: Can be virtual but possible travel to onsite location as needed.
Job Number: 192194
Job Location: Tukwila, WA
Rate: $DOE
Duration: 6 Months
Input Date: 09/17/2021
Last Updated: 11/30/2021
Attention: Dan Mulvihill
Address: 420 CULVER BLVD
City, State: PLAYA DEL REY, CA 90293
Phone: 310/414-7800 X286
800 Phone: 800/927-9318
Fax Phone: 310/414-7808

Previous Listing       Next Listing
Back to Abbreviated Search Results
Back to Complete Search Results
Back to Advanced Job Search

Phone: (425) 806-5200
Fax: (425) 806-5585
ContractJobHunter is a service of: LLC
P.O. Box 3006, Bothell, WA 98041-3006, USA
The content of this website is Copyright 2021 LLC
Terms of Use of ContractJobHunter
Refund Policy
Privacy Policy