Job Listing Description

Elect Design and Analyst Engineer 4

PDS Tech, Inc. is seeking an Elect Design and Analyst Engineer in Hazelwood, MO

  • Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.
  • Leads development of high-level and detailed designs consistent with requirements and specifications.
  • Leads reviews of testing and analysis activity to assure compliance to requirements.
  • Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.
  • Leads activities in support of Supplier Management with make/buy recommendations and other technical services.
  • Coordinates engineering support throughout the lifecycle of the product.
  • Plans research projects to develop concepts for future product designs to meet projected requirements.
  • Works under minimal direction.
  • Leads activities to develop, document and maintain complex architectures, requirements, algorithms, interfaces and designs for Xilinx FPGA based firmware systems.
  • Leads development of code and integration of complex firmware components into a fully functional system.
  • Develops firmware verification plans, test procedures and test environments, executing the test procedures and documenting test results to ensure firmware system requirements are met.
  • Provides technical leadership for firmware projects.
  • Leads development, selection, tailoring and deployment of processes, tools and metrics.
  • Leads firmware research and development projects.
  • Serves as a subject matter expert for firmware domains, system-specific issues, processes and regulations.
  • Tracks and evaluates firmware team performance to ensure product and process conformance to project plans and industry standards.
  • Trains and mentors others. Works under consultative direction.

Basic Qualifications (Required Skills/Experience)
  • Bachelor Degree or higher in Engineering, Mathematics or Physics
  • 6+ years’ of experience in Digital FPGA verification, with design experience
  • Verification work experience using Verilog or SystemVerilog, with UVM methodology

Preferred Qualifications (Desired Skills/Experience)

  • Experience developing Universal Verification Methodology (UVM) compatible testbench components such as predictor, monitor, scorebard and Universal Verification Component (UVC) agents
  • Experience writing UVM virtual sequences and UVC sequences
  • Experience writing SystemVerilog assertion (SVA), and Covergroup/Coverpoints
  • Experience architecting and developing verification methods to verify FPGA level requirements
  • Experience writing simulation plan and generating simulation artifacts
  • Experience in DO-254 verification process
  • Experience in code coverage analysis
  • Experience using Linux or Unix terminal commands
  • Experience with scripting language like Perl and shell script
  • Experience using Revision Control Systems: GIT, BitBucket
  • Experience in running and managing regression, as well as providing regression result traceability to requirements

Job Number: 2110132446
Job Location: Hazelwood, MO
Duration: 12 months
Input Date: 07/15/2021
Attention: Sherine Ibusuki
660 SW 39TH ST STE 215

City, State: RENTON, WA 98057
Phone: 206/763-2840
800 Phone: 800/678-8644
Fax Phone: 206/763-3283

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