Job Listing Description

Design Engineer

PDS Tech, Inc. is seeking a Design Engineer, in Palm Bay, FL.

• Perform preliminary design at the functional block and FPGA level. 
• Code and simulate at the functional block and FPGA level using VHDL. 
• Generate FPGA IP using the Xilinx Vivado tool suite. 
Minimum Qualifications: 
• BSEE (or equivalent) + 4 years applicable FPGA design experience with VHDL 
• Understanding of FPGA design processes including requirements generation, preliminary design, detailed design including code & simulation peer reviews, place & route, timing closure, test plan generation, and integration and test. 
• Understanding of architectural elements within Xilinx 7 series, Ultrascale or Ultrascale+ family FPGAs. 
• Understanding of how VHDL code translates into logic primitives within a Xilinx FPGA. 
• Able to work with a team of designers to generate FPGA solutions. 
• Able to simulate FPGA designs to verify functional performance and code coverage. 
o Experience with Cadence Incisive simulator preferred. 
• Experience with Xilinx Vivado tool suite. 
• Understanding of static timing analysis and the process by which timing closure is achieved. 

Desired Experience: 
• Experience with high speed serial protocols. 
o 10/25 Gb Ethernet, PCI Express Gen 2/3, SRIO, Fibre Channel, XAUI 
• Experience with high speed memory interfaces (DDR3/4). 
• Experience with SOC (Zync 7xxx/UltraScale/UltraScale+) 
• Experience in network protocols including UDP and IPV4/6. 
• Experience integrating with HW/software and supporting the lab integration. 
• Experience testing and qualification of the deliverable system. 
Job Number: 1910108122
Job Location: Palm Bay, FL
Duration: 12 months
Input Date: 02/10/2020
Attention: Elisa Petersen
Address: 11828 W CENTRAL STE 100
City, State: WICHITA, KS 67212-5129
Phone: 316/729-1800
800 Phone: 800/333-8644
Fax Phone: 316/729-1857

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