Job Listing Description

Electrical Engineer Designer - Secret Clearance

Description:
PDS Tech is seeking a candidate for the Electrical Engineer Designer- Secret Clearance position located in Tucson, AZ.  
The Verification Electrical Engineers must be able to develop technical solutions to complex problems that require the regular use of ingenuity and creativity.
As the CDL Department deploys our Universal Verification Methodology (UVM) based verification capability, we need Verification Electrical Engineers to participate in the functional verification of ASICs/FPGAs as-needed.
The Verification Electrical Engineer will create the verification plan with the Program and Register-Transfer Level (RTL) designers input and review in addition to developing the architecture and design of the environment.
This requires creating the necessary run and/or post-processing scripts as well as the overall methodology for the given project in terms of the logistics related to using the verification environment.
You will also participate in a team of engineers to implement the test benches.

The Verification Electrical Engineer will also be involved in the implementation of the verification environment which may include: Creation of Constrained Random Agents; Creation of Monitors, coverage collectors, and Scoreboards; Incorporation of available models that may exist as C/C++, Verilog or VHDL, etc., and/or creation of those models; Creation of functional coverage through use of assertions; Use of functional and code coverage as a quantitative measure to analyze and help determine what is considered 100% coverage for the given design as determined by the verification plan; Writing directed and constrained random tests in parallel with RTL designers to help achieve coverage goals; and use of trouble reports and bug tracking.
Required Skills:
U.S. Citizenship is required - position requires a DoD clearance. Experience with a scripting languages and utilities such as Make, Perl, Python, or Tcl Experience with a HDL languages such as Verilog and VHDL Experience with the HVL language System Verilog Experience with Questa/Modelsim, VCS and/or NCsim
Experience working in a team environment Self-directed
– Able to complete tasks with minimal oversight
Strong written and verbal communication
A minimum of 4 years of applicable experience
Desired Skills:
Experience reading code and performing modifications in either C or C++ and using DPI/PLI/FLI Verification in a DoD-Aerospace environment
Knowledge of embedded systems design using PPC40X, Microblaze, Nios or ARM processors Knowledge of Digital Signal
Processing techniques and implementations
Knowledge of industry standard protocols such as AXI, AMBA, PCIe, Ethernet, SPI, I2C, etc. FPGA design experience using a Linux based development environment

Required Education (including Major):
Bachelor of Science degree in Computer or Electrical Engineering with a minimum of 4 years of relevant experience
Master of Science degree in Computer or Electrical Engineering from an ABET accredited curriculum with a 3.0 GPA or higher and advanced course work related to verification.
 
Job Number: 1710064898
Job Location: Tucson, AZ
Duration: 12 months
Input Date: 03/08/2017
Firm Name: PDS TECHNICAL SERVICES
Attention: David Goodman
Address: 1839 S ALMA SCHOOL RD STE 250
City, State: MESA, AZ 85210
Phone: 480/929-9922
800 Phone: 800/657-0997
Fax Phone: 480/929-9779
Email: cecjphoenix@pdstech.com
Website: https://pdsjobs.force.com/candidates/job_detail_logged_in?id=a1i500000021TvA&URLSource=cjhunter

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