Job Listing Description

Electrical Design and Analysis Engineer 4

PDS Tech, Inc. is seeking a Electrical Design and Analysis Engineer in Tukwila, WA.

  • Within Electronics Development organization (SSED) performs microelectronics technology development for aerospace systems. SSED develops digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other electronic functions.
  • These systems are used on airborne, terrestrial, and satellite platforms.
  • Designs are implemented with state-of-the-art semiconductor process technologies including CMOS, GaAs, GaN, and SiGe.
  • SSED uses external wafer fabrication services but executes the whole design flow in-house (architecture definition, circuit design, RTL, synthesis, physical layout, verification, packaging and testing).
  • SSED owns numerous microelectronics projects, funded both by internal company programs and external U.S. Government Science and Technology (S&T) customers. SSED’s large staff of microelectronics engineers conducts research and designs microelectronics hardware in support of these projects.
  • We are seeking experienced analog/mixed-signal layout design engineer of deep sub-micron CMOS circuits.
  • Experience implementing analog layouts to achieve tight matching, low noise, and low power consumption.
  • Layouts may include analog or digital blocks, resistors, and capacitors, pad IOs, ESD structures, SRAM leaf cells, etc.
  • Proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly.
  • Understanding of IR drop, RC delay, electro migration, self-heating and coupling capacitance management techniques.
  • Proficiency in physical verification including DRC, LVS, and ERC, Support parasitic extraction and analysis.
  • Scripting skills are considered a plus.
  • Good communication skills and ability to work with a cross-functional team
Tasks/responsibilities Include
  • Working closely with the IC design team on layout floor planning and implementation to product finalization
  • From component level layout up to top-level chip assembly
  • Verification including DRC, LVS, and ERC
  • Support parasitic extraction and analysis
  • Drive continued improvement of layout practices and procedures

Key Qualifications:
  • At least 5 years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.
  • Experience implementing analog layouts to achieve optimized matching for low cross talk and reduced parasitic. Layouts may include analog blocks like op-amps, passive such as resistors, capacitors, pad IOs, ESD structures, etc.
  • High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.
  • Must understand techniques for managing IR drop, RC delay, electron-migration, self- heating and coupling capacitance.
  • Must be able to recognize failure prone circuit and layout structures, have experience in applying DFM best practices, and proactively work with circuit designers to identify the best approach to solving problems.
  • High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. reports.
  • Knowledge of CADENCE, MENTOR GRAPHICS and other relevant layout tools.
  • Scripting skills in PERL or SKILL are considered a plus, but not required.
  • Excellent communication skills and can do approach with cross-functional teams.
Education / Experience:  
  • Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience (e.g. PhD+4 years' related work experience, Master+7 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
  • Written and verbal communication of requirements and responsibilities in all platforms
  • 5+ years experience in full-custom analog mixed-signal IC layout
  • Through understanding of industry standard EDA tools from Cadence, Mentor, and Synopsys
  • Standard cell development experience and/or familiarity with structured, pitched, or arrayed layout
  • Experience in layout of FinFET technologies.
  • Knowledge of performance analog and high-power layout techniques
  • Experience exercising and debugging the IC verification flow (DRC, LVS, XOR, PEX, etc.)
  • Demonstrated experience in successfully tapeouts of production IC’s
  • Self-motivated—requiring minimal supervision


Job Number: 2310161856
Job Location: Seattle, WA
Duration: 6 months
Input Date: 03/09/2023
Attention: Sherine Ibusuki
Address: 1839 S ALMA SCHOOL RD STE 250
City, State: MESA, AZ 85210
Phone: 214/647-9600
800 Phone: 800/270-4737

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