The Signal Integrity Engineer will play a critical role in the planning of digital PCB designs, simulation, lab verification, and troubleshooting signal integrity issues on completed designs. They will also be expected to help with design review of critical PCBs for signal integrity concerns. Good communications skills and ability to work with physically dispersed teams is a strong requirement.
Skills Experience Requirements:
- 8+ years’ experience with High-Speed Signal Delivery Design and Evaluation. This includes both signal integrity within a PCB and off the board (board to board connectors, ribbon cables, coaxial cable, etc.).
- Recent experience with Cadence Sigrity design suit or Ansys SIwave for SI simulations is required.
- Expertise in DDRx memory bus designs preferably using Mentor HyperLynx or Cadence Sigrity SI suit is required.
- Expertise in the design of serial links including multilevel signaling (PAM4), COM, jitter analysis and SERDES equalization techniques with CTLE, DFE and FFE is required.
- Expertise in channel model construction of serial links cascading s-parameter data of PCB, connector, and cable to generate a complete system model for an end-to-end simulation.
- At the minimum working level knowledge with Cadence Allegro design layout tool, its constraint manager and schematics is required.
- A high-level knowledge about behavioral device modeling including IBIS and IBIS-AMI models as well as passive device modeling techniques with touchstone files is required.
- A high-level knowledge about SI and PCB design fundamentals including single ended and differential signals, signal loss, impedance control and crosstalk noise is required.
- Experience in the simulation of parallel interfaces including FPGAs, SDRAMs, Flash memory devices is required.
- Experience with Keysight ADS and ANSYS HFSS is a highly desirable asset.
- A good grasp of fundamentals circuit and electromagnetics theory including frequency and time domain analysis techniques, transmission line theory, termination techniques, generating and interpreting data-eye diagrams, bathtub curves with NRZ and PAM4 signaling techniques is required.
- A working knowledge of PCB stackup design with fabrication limitations and cost trade-offs
- along with some experience of high frequency PCB material are required.
- Significant SI lab experience with TDR and VNA measurements is a must.
- The candidate should be able to develop test fixtures for SI measurements (both custom design test boards as well as adhoc probing solutions to troubleshoot existing PCBs)
- Familiarity with the cost vs performance tradeoffs when designing signal interfaces is an asset.
- Experience with high-speed flex circuit design is a desirable asset.
- Bachelor’s degree in Electrical Engineering with emphasis in wireless communications
Occasional overnight travel is required