Job Listing Description

Staff Engineer ASIC/FPGA (VHDL) Designer

Description:
PDS Tech, Inc. is seeking a Staff Engineer ASIC/FPGA (VHDL) Designer, in Redondo Beach, CA.

Summary:
  • VHDL design of ASIC and/or FPGA logic, with an emphasis in Digital Signal Processing
  • FPGA/ASIC verification via simulation and emulation (lab testing), synthesis, timing analysis, and place and route for FPGA
  • FPGA design for Space environment or Space Application


 
 
Qualifications:  
Basic Qualifications: 

  • Bachelor’s Degree in Electrical or Computer Engineering from an accredited institution with minimum of 14+ years of experience with Logic Design in VHDL or Verilog; or 12+ years of experience with Master’s Degree
  • 7+ years of Digital Signal Processing design experience.
  • Well versed in VHDL design for aerospace environment or space application
  • US Citizenship required

Preferred Qualifications:

  • Hands-on lab experience with testing of digital hardware is highly desired.
  • 12 years of Digital Signal Processing design experience.
  •  Must have the ability to obtain and retain an active Security Clearance

 
Job Number: 2010118695
Job Location: Redondo Beach, CA
Duration: 12 months
Input Date: 11/14/2020
Firm Name: PDS TECHNICAL SERVICES
Attention: Chad Dunavant
Address: 370 N WESTLAKE BLVD STE 120
City, State: WESTLAKE VILLAGE, CA 91362
Phone: 805/418-9862
800 Phone: 866/458-4322
Fax Phone: 805/418-9866
Email: cecjwestlake@pdstech.com
Website: https://pdsjobs.force.com/candidates/job_detail?id=a1i1T000003P6KXQA0&URLSource=cjhunter

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