Description: PDS Tech, Inc. is seeking Senior level Electrical or Computer Engineers for our Client, a premier supplier of avionics, electronics, and communications systems.
You will be involved in the testbench design, implementation, and verification of a wide variety of high-performance digital ASICs and FPGAs applied to signal processing, image processing, and information assurance applications.
In this role you will:
Provide verification environment architecture and design using SystemVerilog with OVM/UVM
Create written test cases, code coverage tracking, and functional coverage tracking
Provide testbench development for the verification of RTL blocks using VHDL or SystemVerilog
Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
Experience with testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog
Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
Familiarity with revision control concepts and tools (e.g. Clearcase, Subversion)
Ability to work with minimal supervision, as a part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones
Strong oral and written communication skills and the ability to document and present one's work and status
Ability to obtain a Security Clearance. US Citizenship is required.
Bachelor's Degree in either Electrical Engineering or Computer Engineering field
ASIC / FPGA lab validation with advanced lab equipment
Design for Test (DFT) and manufacturability issues
Experience with Unix, scripting, C/C++, Python, and/or Perl
Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Questasim, Synplify, FPGA-specific tools)