Description: PDS Tech, Inc. is seeking a Sr ASIC Design Engineer 1 for an open position in Cedar Rapids, IA. This position is for an experienced and motivated Senior Electrical or Computer engineering experienced candidate to be involved in the design, implementation, verification and integration of a wide variety of high-performance digital ASICs and FPGAs applied to signal processing and information assurance applications.
Key Responsibilities will include: -Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration -RTL coding and simulation in VHDL or Verilog -Testbench development for the verification of RTL blocks using VHDL or SystemVerilog -Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
This position requires these skills and abilities: -RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using VHDL or SystemVerilog -Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure -Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGA-specific tools) -Familiarity with revision control concepts and tools (e.g. Subversion) -Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones -Strong oral and written communication skills and the ability to document and present one's work and status -Ability to obtain a US DOD Security Clearance. US Citizenship is required. -Bachelor's Degree in applicable engineering field
Desired skills of a successful candidate: -Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog) -ASIC / FPGA lab validation with advanced lab equipment -Design for Test (DFT) and manufacturability issues -Experience with Unix, scripting, C/C++, and/or Perl