Job Listing Description

THIS JOB IS NO LONGER AVAILABLE. THIS IS ARCHIVAL INFORMATION.
FPGA/ASIC Designer - Secret Clearance Required

Description:
FPGA/ASIC Designer - Secret Clearance Required

Location: Orlando, FL & Remote

Job ID: #62072



Citizenship Requirement: U.S. Citizen

Security Clearance Level:  Secret with background investigation in last 6 years (S-6)

Min years of experience:

11 with B.Sc. or 9 with M.Sc.

Degree Requirements: B.Sc. in Electrical Engineering or Computer Engineering



Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results.



Seeking Electrical Engineer with DFT (Design for Test)/ DFD (Design for Debug) / DFM (Design For Manufacture) experience. The successful candidate will be responsible for the design, implementation, and verification of DFT/DFD/DFM, as well as mentoring and growing talent in the discipline. This individual will be considered a Subject Matter Expert (SME) in techniques such as Scan, MBIST/MBISR, Boundary Scan, ATPG, Logical Equivalence Checking, and Gate Level Simulation.



Successful candidate will work with the digital design and physical implementation teams to capture DFT requirements, develop and implement DFT architecture, work with the verification team to verify DFT implementations, generate structural test vectors, analyze and improve coverage/test time/test cost, work with designers on Static Timing Analysis (STA), physical, power and logical issues impacting DFT, work with Integration & Test as well as Foundry representatives to bring up test vectors on silicon, and develop and execute schedules related to these tasks.



Typical Minimums:

Bachelors degree from an accredited college in a related discipline, or equivalent experience/combined education, with 14 years or more of professional experience; or 12 years of professional experience with a related Masters degree. Considered an expert, authority in discipline.



Basic Qualifications:

• Secret plus 6 year background investigation (S-6)

• Bachelor’s Degree in Electrical Engineering or Computer Engineering with 11+ years of professional DFT experience or 9+ years of experience with a related Masters degree

• Industrial standards and practices in DFT, including ATPG, JTAG, MBIST/MBISR and trade-offs between test quality and test time

• Developing DFT specifications

• Industry standard DFT and design tools

• Debugging ATPG/MBIST patterns

• STA constraints and their interaction with DFT



Desired Skills:

• Experience with Synopsys or Cadence DFT tools

• Experience with JTAG and IEEE standards 1149.1 and 1149.6.









____________________________________________________________________

Butler America Aerospace, LLC. is proud to provide an equal opportunity workplace and be an affirmative action employer. Consider Butler because we are committed to hiring and retaining a diverse workforce. We recognize that we thrive on diversity for the benefit of our employees, our customers, and the communities where we are located. Employment with Butler America Aerospace, LLC. is governed on the basis of qualifications and competence without regard to race, color, religion, gender, national origin, ethnicity, veteran status, disability status, age, sexual orientation, gender identity, gender expression, marital status, mental or physical disability or any other legally protected status.
 
Job Number: 62072
Job Location: Orlando, FL
Per Diem: Possible
Start Date: ASAP
Input Date: 09/02/2021
Firm Name: BUTLER AEROSPACE & DEFENSE
Attention: David Surreira
Address: SHELTON POINTE STE 204
2 TRAP FALLS ROAD

City, State: SHELTON, CT 06484
Phone: 203/926-2705
Website: www.butler.com

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