Job Listing Description

ASIC/FPGA (VHDL) Designer - Many Needed

- Bachelor’s Degree in Electrical or Computer Engineering from an accredited institution with minimum of 9 years of experience with Logic Design in VHDL or Verilog; or 7 years of experience with Masters Degree
- Must have the ability to obtain and maintain an active Government clearance

Preferred Qualifications:
- Hands-on lab experience with testing of digital hardware is highly desired
- Experience with Digital Signal Processing (DSP)
- 10 years or more of digital Logic Experience
- Security Clearance (any level)

Email resume to:
Job Number: North-CA-ASIC
Job Location: Redondo Beach, CA
Rate: $72.00-$80.00/hour
Per Diem: Possible
Overtime: Possible
Duration: 12 Months+
Start Date: ASAP
Input Date: 09/08/2020
Last Updated: 09/22/2020
Attention: Mary Ann McCarthy
Address: 1215 FERN RIDGE PKWY STE 231
City, State: ST LOUIS, MO 63141
Phone: 314/628-9143
800 Phone: 800/472-3737
Fax Phone: 314/628-9485

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