Job Listing Description

ASIC/FPGA Design Engineer

Chipton-Ross is seeking an ASIC/FPGA Design Engineer for an opening in Camden, NJ.

The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. S/he will develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL, HLS) with high speed protocols– NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs. Additionally S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. Client has deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS). This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security.

At least 3 year experience with proven track record of implementing complex algorithms in networking ASIC/FPGAs
Proficiency in VHDL, C++ (OOP) and System Verilog Assertions (SVA) Experience with debugging in ARM ecosystem with Linux OS Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet) Excellent Analytical/Debug skills Good verbal, written, and presentation skills

A PLUS for prior experience with: High Level Synthesis (HLS) with Vivado, Mentor Catapult Xilinx MPSOC, and Vivado SDK and Linux super user Cryptographic and high speed networking designs

Accredited Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred

9/80, 1st Shift

MISCELLANEOUS: Applicants responding to this position will be subject to a government security investigation and must meet eligibility requirements by currently possessing the ability to view classified government information.
Job Number: 179061
Job Location: Camden, NJ
Rate: Up to $120.00 DOE
Duration: 7 Months
Input Date: 05/15/2019
Attention: Robert Davis
Address: 343 MAIN ST
City, State: EL SEGUNDO, CA 90245
Phone: 310/414-7800 X286
800 Phone: 800/927-9318
Fax Phone: 310/414-7808

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