Job Listing Description

FPGA UVM Verification Engineer 

PDS Tech, Inc. is seeking a FPGA UVM Verification Engineer, in Palm Bay, FL.

• Create UVM chip level verification environments for multiple FPGAs 
• Develop reusable agents, top level testbench modules and environments 
• Develop scoreboards and predictors based upon DUT requirements 
• Define and implement functional coverage model based upon DUT requirements 
• Verification of control and data plane functionality 
• Verify existing interface protocol modules retargeted to different FPGA vendor/architectures. 
• Role might additionally require some limited module level design work in VHDL 
• Document and execute test plan, and debug module- and chip-level tests 
• Develop and run regression tests 
Minimum Qualifications: 
• Expertise in UVM and SystemVerilog required 
• 8+ years FPGA/ASIC verification experience. 
• At least 3 successfully completed full FPGA UVM verification cycles. 
• Self-motivated, strong communications skills, schedule-conscious, and team-oriented 
• BSEE or equivalent, MSEE preferred 

Desired Qualifications: 
• Cadence simulation tool and flow expertise 
• Xilinx, Altera, Microsemi tool chain experience is a plus 
• Strong domain knowledge of PCIe, 10Gb Ethernet (IPv4, TCP/UDP), Fibre Channel, IEEE1394, AHB/AXI, DDR4 
Job Number: 1910106844
Job Location: Palm Bay, FL
Duration: 12 months
Input Date: 11/06/2019
Attention: Hemant Sachdev
Address: 3130 S HARBOR BLVD STE 100
City, State: SANTA ANA, CA 92704
Phone: 714/540-7900
800 Phone: 800/234-8644
Fax Phone: 714/540-8092

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