Job Listing Description

THIS JOB IS NO LONGER AVAILABLE. THIS IS ARCHIVAL INFORMATION.
Elect Design and Analy Engr 3 (ASIC/FPGA design and verification engineer)

Description:
Elect Design and Analy Engr 3

Location: El Segundo, CA
Duration: 1 year

Job Description:
The Client Company's Electronic Products organization is seeking experienced (level 3) digital ASIC/FPGA design and verification engineers to support multiple product lines based in Los Angeles, CA.

Responsibilities:
- Utilize high-level architectural documentation along with algorithm description and implement DSP functions for functions such as decimation, interpolation, general filtering, up-down conversion, digital beamforming, channelization, and be able to develop mathematical models in SystemVerilog to verify design implementation and develop and run scripts and Makefiles.
- Utilize understanding of system requirements to architect block level design specifications
- Prepare detailed design documentation
- HDL coding, logical equivalency checking, static timing analysis, CDC, linting
- Integration of third-party IP
- Create self-checking and reusable testbenches from scratch
- Develop Functional Coverage Models and Closing Code Coverage

Required Qualifications:
- Minimum of 3 years experience in Digital ASIC design and verification
- Experience with ASIC development including architectural definition, and detailed design implementation and functional verification using SystemVerilog
- Experience with design architecture and detailed specification generation

Preferred Skills:
- Self-Starter: Demonstrated ability to learn and apply new concepts quickly
- Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
- Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
- Knowledge and competency in UVM: Ability to create drivers, monitors, predictors, and scoreboards
- Ability to create self-checking and reusable testbenches from scratch
- Experience developing Functional Coverage Models and Closing Code Coverage
- Proficient in scripting languages: Make, Perl, Python, etc.
- Revision Control Systems: svn, cvs, git
- Proficient in Linux Environments
- Thrive in working within a fast-paced environment and work well in a team of ASIC engineers and Subsystem engineers
- Demonstrated history of 1st pass success with ASIC designs

Typical Education and Experience:
Degree and typical experience in engineering classification: Bachelor's and 5 or more years' experience, Master's degree with 3 or more years' experience or PhD degree with experience. Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry. ABET is the preferred, although not required, accreditation standard.

SSBI Clearance Preferred but not required.

Education / Experience:
Degree and typical experience in engineering classification: Bachelor's and 5 or more years' experience, Master's degree with 3 or more years' experience or PhD degree with experience. Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry. ABET is the preferred, although not required, accreditation standard.

Skill Code:
64Y-Microelectronics

######If interested then please share updated resume at ravi@iconma.com ######

Job Number: 18-04660
Job Location: El Segundo,, CA
Input Date: 11/14/2020

Firm Name: ICONMA LLC
Attention: Ravi Kumar
Address: 850 STEPHENSON HWY STE 612
City, State: TROY, MI 48083
Website: www.iconma.com

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