Job Listing Description

THIS JOB IS NO LONGER AVAILABLE. THIS IS ARCHIVAL INFORMATION.
ASIC/FPGA Design Verification Engineer

Description:
Required Skills:
• 5+ years of experience
• 1-2 years of UVM tool
• Cadence Xcelium verification tool
• Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.

Job Location: El Segundo, CA, CA
Rate: Hourly
Per Diem: NA
Overtime: NA
Duration: 06 Months
Input Date: 08/12/2024

Firm Name: RANG TECHNOLOGIES INC
Attention: Rahul Mehar
Address: 15 CORPORATE PL S STE 356
City, State: PISCATAWAY, NJ 08854
Phone: 732/947-4119
Website: www.rangtech.com

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