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THIS JOB IS NO LONGER AVAILABLE. THIS IS ARCHIVAL INFORMATION.
FPGA UVM Verification Engineer

Description:
Responsibilities:
• Create UVM chip level verification environments for multiple FPGAs
• Develop reusable agents, top level testbench modules and environments
• Develop scoreboards and predictors based upon DUT requirements
• Define and implement functional coverage model based upon DUT requirements
• Verification of control and data plane functionality
• Verify existing interface protocol modules retargeted to different FPGA vendor/architectures.
• Role might additionally require some limited module level design work in VHDL
• Document and execute test plan, and debug module- and chip-level tests
• Develop and run regression tests

Minimum Qualifications:
Expertise in UVM and SystemVerilog required

• 8+ years FPGA/ASIC verification experience.
• At least 3 successfully completed full FPGA UVM verification cycles.
• Self-motivated, strong communications skills, schedule-conscious, and team-oriented
• BSEE or equivalent, MSEE preferred

Desired Qualifications:
• Cadence simulation tool and flow expertise
• Xilinx, Altera, Microsemi tool chain experience is a plus
• Strong domain knowledge of PCIe, 10Gb Ethernet (IPv4, TCP/UDP), Fibre Channel, IEEE1394, AHB/AXI, DDR4

Nesco Resource is an equal employment opportunity employer and does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, or veteran status, or any other legally protected characteristics with respect to employment opportunities.
 
Job Number: 19-39816
Job Location: Palm Bay, FL
Rate: Hourly
Per Diem: Split
Overtime: Possible
Input Date: 11/14/2020
Firm Name: NESCO RESOURCE
Attention: Robert Mihalyi
Address: 101 COMMERCE ST STE 3001
City, State: LAKE MARY, FL 32746
Phone: 407/710-8000
Fax Phone: 407/710-8001
Website: www.nescoresource.com
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