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THIS JOB IS NO LONGER AVAILABLE. THIS IS ARCHIVAL INFORMATION.
Staff Engineer ASIC/FPGA (VHDL) Designer CA

Description:
Staff Engineer ASIC/FPGA (VHDL) Designer (Job Number: 20004560)
Number of Openings: 4
Location(s): United States-California-Redondo Beach

Shift: 1st Shift
Target Start Date: Mar 30, 2020
Target End Date: Mar 26, 2021

Pay Rate: $90/hr
Work Schedule: 9/80
Duration of Assignment: Up to 1 year

This position is based at our Space Park campus in Redondo Beach, CA. Duties include VHDL design of ASIC and/or FPGA logic, verification via simulation and emulation (lab testing), synthesis, and timing analysis.

Additional responsibilities include:
Designs and develops circuits used in electronic devices. device evaluation and characterization, test box design, prototype construction and checkout, and determination of wafer fabrication processes. Prepares test methods and specifications; analyzes equipment to establish operating data and conducts experimental tests; provides finished device approval; and prepares customer application information.

Basic Qualifications:
- Bachelor’s Degree in Electrical or Computer Engineering from an accredited institution with minimum of 14 years of experience with Logic Design in VHDL or Verilog; or 12 years of experience with Masters Degree

Preferred Qualifications:
- Hands-on lab experience with testing of digital hardware is highly desired
- Experience with Digital Signal Processing (DSP)
- 15 years or more of digital Logic Experience

Job Number: JK-1848ATO
Job Location: Redondo Beach, CA
Rate: 90/hr max
Per Diem: pd split possible
Duration: 12 months
Input Date: 11/14/2020

Firm Name: MIDCOM CORPORATION
Attention: Jeana Edrozo
Address: 1275 N MANASSERO ST
City, State: ANAHEIM, CA 92807
Phone: 714/630-1999
800 Phone: 800/737-1632
Fax Phone: 714/459-7055
Website: www.midcom.com


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