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THIS JOB IS NO LONGER AVAILABLE. THIS IS ARCHIVAL INFORMATION.
Staff Engineer ASIC/FPGA (VHDL) Designer - Excellent Rates - Many Needed

Description:
Seeking a motivated candidate to work implementation of Digital Communication Designs for space applications.
VHDL design of ASIC and/or FPGA logic, with an emphasis in Digital Signal Processing
FPGA/ASIC verification via simulation and emulation (lab testing), synthesis, timing analysis, and place and route for FPGA
FPGA design for Space environment or Space Application

Basic Qualifications:

Bachelor’s Degree in Electrical or Computer Engineering from an accredited institution with minimum of 14+ years of experience with Logic Design in VHDL or Verilog; or 12+ years of experience with Master’s Degree

7+ years of Digital Signal Processing design experience.

Well versed in VHDL design for aerospace environment or space application

Hands-on lab experience with testing of digital hardware is highly desired.

12 years of Digital Signal Processing design experience.

Must have the ability to obtain and retain an active Security Clearance

Email resume to: mmccarthy@pdstech.com

Job Number: ASIC/FPGA
Job Location: Redondo Beach, CA
Rate: $90.00-$110.00/hour
Per Diem: Possible
Overtime: Possible
Duration: Long Term
Start Date: ASAP
Input Date: 11/14/2020

Firm Name: PDS TECH COMMERCIAL, INC
Attention: Mary Ann McCarthy
Address: 1215 FERN RIDGE PKWY STE 231
City, State: ST LOUIS, MO 63141
Phone: 314/628-9143
800 Phone: 800/472-3737
Fax Phone: 314/628-9485
Website: www.pdstech.com


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